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VND5E160AJ-E
Double channel high side driver with analog current sense for automotive applications
Features
Max transient supply voltage Operating voltage range Max On-state resistance (per ch.) Current limitation (typ.) Off state supply current
1. Typical value with all loads connected.
VCC VCC RON ILIMH IS
41 V 4.5 to 28V 160 m 10 A 2 A(1)
PowerSSO-12
- Reverse battery protected (see Application schematic) - Electrostatic discharge protection
General - Inrush current active management by power limitation - Very low stand-by current - 3.0 V CMOS compatible inputs - Optimized electromagnetic emissions - Very low electromagnetic susceptibility - In compliance with the 2002/95/EC european directive - Very low current sense leakage Diagnostic functions - Proportional load current sense - High current sense precision for wide currents range - Current sense disable - Off state openload detection - Output short to VCC detection - Overload and short to ground (power limitation) indication - Thermal shutdown indication Protections - Undervoltage shutdown - Overvoltage clamp - Load current limitation - Self limiting of fast thermal transients - Protection against loss of ground and loss of VCC - Over-temperature shutdown with autorestart (thermal shutdown)
March 2008
Application

All types of resistive, inductive and capacitive loads Suitable as LED driver
Description
The VND5E160AJ-E is a single channel high-side driver manufactured in the ST proprietary VIPower M0-5 technology and housed in the tiny PowerSSO-12 package. The VND5E160AJ-E is designed to drive 12V automotive grounded loads delivering protection, diagnostics and easy 3V and 5V CMOS compatible interface with any microcontroller. The device integrates advanced protective functions such as load current limitation, inrush and overload active management by power limitation, over-temperature shut-off with auto-restart and over-voltage active clamp. A dedicated analog current sense pin is associated with every output channel in order to provide Ehnanced diagnostic functions including fast detection of overload and short-circuit to ground through power limitation indication, overtemperature indication, short-circuit to Vcc diagnosis and ON & OFF state open load detection. The current sensing and diagnostic feedback of the whole device can be disabled by pulling the CS_DIS pin high to allow sharing of the external sense resistor with other similar devices.
Rev 2
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Contents
VND5E160AJ-E
Contents
1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 2.4 2.5 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 24
3.1.1 3.1.2 Solution 1 : resistor in the ground line (RGND only) . . . . . . . . . . . . . . . 24 Solution 2 : diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . 25
3.2 3.3 3.4 3.5
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.4.1 Short to VCC and OFF state open load detection . . . . . . . . . . . . . . . . . 27
Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 28
4
Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1 5.2 5.3 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6 7
Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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VND5E160AJ-E
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC=13V, Tj=25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Current sense (8V3/37
List of figures
VND5E160AJ-E
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Openload Off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Iout/ Isense vs. Iout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Overload or Short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Intermittent Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 OFF-State Open Load with external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Short to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TJ evolution in Overload or Short to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 On state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 On state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Maximum turn-Off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 28 PowerSSO-12 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). . . . . . . . 29 PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON). . . . . 30 Thermal fitting model of a double channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . 30 PowerSSO-12 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PowerSSO-12 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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VND5E160AJ-E
Block diagram and pin description
1
Block diagram and pin description
Figure 1. Block diagram
VCC S ignal C lamp
Undervoltage
C ontrol & Diagnostic 1
P ower C lamp
IN1 IN2
DR IVE R V ON Limitation Over temp. C urrent Limitation OFF S tate Open load V SENS EH C urrent S ense CH 1
C ONTROL & DIAG NOS TIC C hannels 2
CH 2
CS_ DIS
CS1 CS2
OUT2 OUT1
LOG IC
OVE R LOAD P R OTE C TION (AC TIVE P OWE R LIMITATION)
G ND
Table 1.
Pin function
Function Battery connection. Power output. Ground connection. Must be reverse battery protected by an external diode/resistor network. Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state.
Name VCC OUTPUTn GND INPUTn
CURRENT SENSEn Analog current sense pin, delivers a current proportional to the load current. CS_DIS Active high CMOS compatible pin, to disable the current sense pin.
5/37
Block diagram and pin description Figure 2. Configuration diagram (top view)
VND5E160AJ-E
TAB = Vcc GND INPUT2
INPUT1
CURRENT SENSE1 CURRENT SENSE2 CS_DIS
1 2 3 4 5 6
12 11 10 9 8 7
N.C. OUTPUT2 OUTPUT2 OUTPUT1 OUTPUT1 N.C.
PowerSSO-12
Table 2.
Suggested connections for unused and not connected pins
Current sense Not allowed Through 1k resistor N.C. X X Output X Through 22k resistor Input X Through 10k resistor CS_DIS X Through 10k resistor
Connection / pin Floating To ground
6/37
VND5E160AJ-E
Electrical specifications
2
Electrical specifications
Figure 3. Current and voltage conventions
IS VCC VFn ICSD VCSD IIN1 VIN1 IIN2 VIN2 INPUT2 GND CURRENT SENSE2 ISENSE2 VSENSE2 INPUT1 CS_DIS OUTPUT1 CURRENT SENSE1 OUTPUT2 IOUT1 VOUT1 ISENSE1 VSENSE1 IOUT2 VOUT2 VCC
IGND
Note:
VFn = VOUTn - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 3.
Symbol VCC -VCC - IGND IOUT - IOUT IIN ICSD DC supply voltage Reverse DC supply voltage DC reverse ground pin current DC output current Reverse DC output current DC input current DC current sense disable input current
Absolute maximum ratings
Parameter Value 41 0.3 200 Internally limited 6 -1 to 10 -1 to 10 200 VCC-41 +VCC Unit V V mA A A mA mA mA V V
-ICSENSE DC reverse CS pin current VCSENSE Current sense maximum voltage
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Electrical specifications Table 3.
Symbol EMAX
VND5E160AJ-E
Absolute maximum ratings (continued)
Parameter Maximum switching energy (single pulse) (L=12mH; RL=0; Vbat=13.5V; Tjstart=150C; IOUT = IlimL(Typ.) ) Electrostatic discharge (Human Body Model: R=1.5K; C=100pF) - INPUT - CURRENT SENSE - CS_DIS - OUTPUT - VCC Charge device model (CDM-AEC-Q100-011) Junction operating temperature Storage temperature Value 34 Unit mJ
VESD
4000 2000 4000 5000 5000 750 -40 to 150 -55 to 150
V V V V V V C C
VESD Tj Tstg
2.2
Thermal data
Table 4.
Symbol
Thermal data
Parameter Max. value 8 See Figure 36 Unit C/W C/W
Rthj-case Thermal resistance junction-case (With one channel ON) Rthj-amb Thermal resistance junction-ambient
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VND5E160AJ-E
Electrical specifications
2.3
Electrical characteristics
Values specified in this section are for 8VSymbol VCC VUSD VUSDhyst
Power section
Parameter Operating supply voltage Undervoltage shutdown Undervoltage shutdown hysteresis On state resistance (1) Clamp voltage Supply current IOUT= 1A; Tj= 25C IOUT= 1A; Tj= 150C IOUT= 1A; VCC= 5V; Tj= 25C IS= 20 mA Off State; VCC= 13V; Tj= 25C; VIN=VOUT=VSENSE=VCSD=0V On State; VCC=13V; VIN=5V; IOUT=0A VIN=VOUT=0V; VCC=13V; Tj=25C VIN=VOUT=0V; VCC=13V; Tj=125C -IOUT= 0.6A; Tj=150C 0 0 41 46 2(2) 3 0.01 Test conditions Min. Typ. Max. Unit 4.5 13 3.5 0.5 160 320 210 52 5(2) 6 3 5 0.7 28 4.5 V V V m m m V A mA A V
RON Vclamp IS
IL(off1) VF
Off state output current (1) Output - VCC diode voltage (1)
1. For each channel. 2. PowerMOS leakage included.
Table 6.
Symbol td(on) td(off) (dVOUT/dt)on (dVOUT/dt)off WON WOFF
Switching (VCC=13V, Tj=25C)
Parameter Turn- On delay time Turn- Off delay time Turn- On voltage slope Turn- Off voltage slope Switching energy losses during twon Switching energy losses during twoff Test conditions RL= 13 (see Figure 6.) RL= 13 (see Figure 6.) RL= 13 RL= 13 RL= 13 (see Figure 6.) RL= 13 (see Figure 6.) Min. Typ. 10 15 See Figure 26. See Figure 28. 0.03 0.02 Max. Unit s s V/s V/s mJ mJ
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Electrical specifications Table 7.
Symbol VIL IIL VIH IIH VI(hyst) VICL VCSDL ICSDL VCSDH ICSDH
VND5E160AJ-E
Logic inputs
Parameter Input low level voltage Low level input current Input high level voltage High level input current Input hysteresis voltage Input clamp voltage CS_DIS low level voltage Low level CS_DIS current CS_DIS high level voltage High level CS_DIS current VCSD= 2.1V 0.25 ICSD= 1mA ICSD= -1mA 5.5 -0.7 7 VCSD= 0.9V 1 2.1 10 IIN= 1mA IIN= -1mA VIN= 2.1V 0.25 5.5 -0.7 0.9 7 VIN= 0.9V 1 2.1 10 Test conditions Min. Typ. Max. 0.9 Unit V A V A V V V V A V A V V V
VCSD(hyst) CS_DIS hysteresis voltage VCSCL CS_DIS clamp voltage
Table 8.
Symbol IlimH IlimL TTSD TR TRS THYST VDEMAG
Protections and diagnostics (1)
Parameter DC short circuit current Short circuit current during thermal cycling Shutdown temperature Reset temperature Thermal reset of STATUS Thermal hysteresis (TTSD-TR) Turn-Off output voltage clamp Output voltage drop limitation Test conditions VCC= 13V 5V2.5 175
TRS + 1 TRS + 5 135
VON
25
mV
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.
10/37
VND5E160AJ-E Table 9.
Symbol K0
Electrical specifications Current sense (8VParameter IOUT/ISENSE Test conditions Min. Typ. Max. Unit
IOUT= 0.025A; VSENSE= 0.5V; VCSD=0V; 270 Tj= -40C...150C IOUT= 0.35A; VSENSE=0.5V; VCSD=0V; Tj= -40C...150C IOUT=0.35A; VSENSE=0.5V; VCSD=0V; Tj= 25C...150C 345 370 -13
520 470 470
730 610 540 13 %
K1
IOUT/ISENSE
dK1/K1
(1)
IOUT= 0.35A; VSENSE= 0.5V; Current sense ratio VCSD=0V; drift TJ= -40 C to 150 C IOUT= 0.5A; VSENSE= 4V; VCSD= 0V; Tj= -40C...150C IOUT= 0.5A; VSENSE= 4V; VCSD= 0V; Tj= 25C...150C
K2
IOUT/ISENSE
370 390 -8
460 460
550 510 8 %
dK2/K2(1)
IOUT= 0.5 A; VSENSE= 4 V; Current sense ratio VCSD= 0V; drift TJ= -40 C to 150 C IOUT= 1.5A; VSENSE=4V; VCSD=0V; Tj= -40C...150C IOUT=1.5A; VSENSE=4V; VCSD=0V; Tj= 25C...150C
K3
IOUT/ISENSE
400 410 -4
430 430
470 460 4 %
dK3/K3(1)
IOUT= 1.5 A; VSENSE= 4 V; Current sense ratio VCSD=0V; drift TJ= -40 C to 150 C IOUT=0A; VSENSE=0V; VCSD=5V; VIN=0V; Tj=-40C...150C VCSD=0V; VIN=5V; Tj=-40C...150C IOUT=0.6A; VSENSE=0V; VCSD=5V; VIN=5V; Tj= -40C...150C
ISENSE0
Analog sense leakage current
0 0
1 2
A A
0 1
1 5
A mA
IOL
Openload ON state current detection threshold Max analog senseoutput voltage
VIN = 5V, 8VVSENSE
5
V
Analog sense VSENSEH(2) output voltage in fault condition ISENSEH(2) Analog sense output current in fault condition
VCC=13V; RSENSE= 3.9K;
8
V
VCC=13V; VSENSE= 5V;
9
mA
11/37
Electrical specifications Table 9.
Symbol
VND5E160AJ-E
Current sense (8VParameter Delay response time from falling edge of CS_DIS pin Delay response time from rising edge of CS_DIS pin Delay response time from rising edge of INPUT pin Test conditions VSENSE<4V, 0.08AtDSENSE1H
40
100
s
tDSENSE1L
5
20
s
tDSENSE2H
30
150
s
Delay response time between rising edge of output tDSENSE2H current and rising edge of current sense tDSENSE2L Delay response time from falling edge of INPUT pin
110
s
80
250
s
1. Parameter guaranteed by design; it is not tested. 2. Fault condition includes: power limitation, overtemperature and open load OFF state detection.
Table 10.
Symbol VOL
Openload detection (8VParameter Openload Off state voltage detection threshold Output short circuit to VCC detection delay at turn Off Off state output current at VOUT = 4V Off state output current at VOUT = 2V Delay response from output rising edge to VSENSE rising edge in open-load Test conditions VIN = 0 V Min. 2 Typ. See Figure 5 Max. 4 Unit V
tDSTKON
See Figure 5 VIN=0V; VSENSE=0V VOUT rising from 0V to 4V VIN=0V; VSENSE=VSENSEH VOUT falling from VCC to 2V VOUT= 4 V; VIN= 0V VSENSE= 90% of VSENSEH
180
1200
s
IL(off2)r IL(off2)f
-120 -50
0 90
A A
td_vol
20
s
12/37
VND5E160AJ-E Figure 4.
INPUT CS_DIS LOAD CURRENT SENSE CURRENT tDSENSE2H tDSENSE1L
Electrical specifications Current sense delay characteristics
tDSENSE1H
tDSENSE2L
Figure 5.
Openload Off-state delay timing
OUTPUT STUCK TO VCC VIN
VOUT > VOL VSENSEH
VCS tDSTKON
Figure 6.
Switching characteristics
VOUT tWon 80% dVOUT/dt(on) tr 10% tf t INPUT td(on) td(off) tWoff 90% dVOUT/dt(off)
t
13/37
Electrical specifications Figure 7.
VND5E160AJ-E
Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled)
VIN
tDSENSE2H
t IOUT
IOUTMAX
90% IOUTMAX
t ISENSE
ISENSEMAX
90% ISENSEMAX
t
Figure 8.
Output voltage drop limitation
Vcc-Vout Tj=150oC Tj=25oC Tj=-40oC
Von Iout Von/Ron(T)
14/37
VND5E160AJ-E Figure 9.
700 650 600 550 500 450 400 350 300 250 200 0,35
min Tj = 25 C to 150 C typical value max Tj = -40 C to 150 C max Tj = 25 C to 150 C
Electrical specifications Iout/ Isense vs. Iout
Iout / Isense
min Tj = -40 C to 150 C
0,58
0,81
1,04
1,27
1,5
IOUT (A)
Figure 10. Maximum current sense ratio drift vs load current
dk/k(%)
15 10 5 0 -5 -10 -15 0,35
0,58
0,81
1,04
1,27
1,5
IOUT (A)
Note:
Parameter guaranteed by design; it is not tested.
15/37
Electrical specifications Table 11. Truth table
Input L H L H L H H Overload H L H L L H L Output L H L L L L X (no power limitation) Cycling (power limitation) L L H H H L
VND5E160AJ-E
Conditions Normal operation Overtemperature Undervoltage
Sense (VCSD=0V)(1) 0 Nominal 0 VSENSEH 0 0 Nominal VSENSEH 0 VSENSEH VSENSEH VSENSEH < Nominal 0
Short circuit to GND (Power limitation) Open load OFF State (with external pull up) Short circuit to VCC (external pull up disconnected) Negative output voltage clamp
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit.
16/37
VND5E160AJ-E Table 12.
ISO 7637-2: 2004(E) Test pulse 1 2a 3a 3b 4 5b
(2)
Electrical specifications Electrical transient requirements
Test levels(1) III -75V +37V -100V +75V -6V +65V IV -100V +50V -150V +100V -7V +87V Number of pulses or test times 5000 pulses 5000 pulses 1h 1h 1 pulse 1 pulse Burst cycle/pulse repetition time Min. 0.5s 0.2s 90ms 90ms Max. 5s 5s 100ms 100ms 2 ms, 10 50s, 2 0.1s, 50 0.1s, 50 100ms, 0.01 400ms, 2 Delays and Impedance
ISO 7637-2: 2004E Test pulse 1 2a 3a 3b 4 5b(2)
Test level results III C C C C C C VI C C C C C C
Class C E
Contents All functions of the device performed as designed after exposure to disturbance. One or more functions of the device did not perform as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. 2. Valid in case of external load dump clamp: 40V maximum referred to ground.
17/37
Electrical specifications
VND5E160AJ-E
2.4
Waveforms
Figure 11. Normal operation
Normal operation
INPUT Nominal load Nominal load
IOUT
VSENSE
VCS_DIS
Figure 12. Overload or Short to GND
Overload or Short to GND
INPUT ILimH > IOUT
Power Limitation Thermal cycling ILimL >
VSENSE
VCS_DIS
18/37
VND5E160AJ-E Figure 13. Intermittent Overload
Electrical specifications
Intermittent Overload
INPUT ILimH > IOUT VSENSEH> VSENSE
Overload ILimL > Nominal load
VCS_DIS
Figure 14. OFF-State Open Load with external circuitry
OFF-State Open Load with external circuitry
INPUT VOUT > VOL VOUT VOL
IOUT VSENSEH > tDSTK(on) VSENSE
VCS_DIS
19/37
Electrical specifications Figure 15. Short to VCC
VND5E160AJ-E
Short to VCC
Resistive Short to VCC Hard Short to VCC
VOUT
VOL
VOUT > VOL
IOUT tDSTK(on) tDSTK(on)
VCS_DIS
Figure 16. TJ evolution in Overload or Short to GND
TJ evolution in Overload or Short to GND
INPUT
Self-limitation of fast thermal transients
TTSD TR
THYST
TJ_START TJ ILimH > Power Limitation
< ILimL IOUT
20/37
VND5E160AJ-E
Electrical specifications
2.5
Electrical characteristics curves
Figure 18. High level input current
Iih (A)
5 4,5 250
Figure 17. Off state output current
Iloff (nA)
300
200
Off State Vcc=13V Vin=Vout=0V
Vin=2.1V
4 3,5 3
150
2,5 2
100
1,5 1 0,5
50
0 -50 -25 0 25 50 75 100 125 150 175
0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 19. Input clamp voltage
Vicl (V)
7 6,8
Figure 20. Input low level
Vil (V)
2 1,8
lin=1mA
6,6 6,4 6,2 6 5,8 5,6 5,4 5,2 5 -50 -25 0 25 50 75 100 125 150 175 1,6 1,4 1,2 1 0,8 0,6 0,4 0,2 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 21. Input high level
Vih (V)
4 3,5 3
Figure 22. Input hysteresis voltage
Vihyst (V)
1 0,9 0,8 0,7
2,5 2 1,5 1
0,6 0,5 0,4 0,3 0,2
0,5 0 -50 -25 0 25 50 75 100 125 150 175
0,1 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
21/37
Electrical specifications
VND5E160AJ-E
Figure 23. On state resistance vs. Tcase
Ron (mOhm)
300
Figure 24. On state resistance vs. VCC
Ron (mOhm)
300
250
Iout= 1A Vcc=13V
Tc=150C
250
Tc=125C
200
200
150
150
Tc=25C
100
100
Tc=-40C
50 -50 -25 0 25 50 75 100 125 150 175
50 0 5 10 15 20 25 30 35 40
Tc (C)
Vcc (V)
Figure 25. Undervoltage shutdown
Vusd (V)
16 14 12
Figure 26. Turn-On voltage slope
(dVout/dt )On (V/ms)
1000 900 800 700
Vcc=13V RI=13 Ohm
10 8 6 4
600 500 400 300 200
2 0 -50 -25 0 25 50 75 100 125 150 175
100 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 27. ILIMH vs. Tcase
Ilimh (A)
20
Figure 28. Turn-Off voltage slope
(dVout/dt )Off (V/ms)
1400 1300
Vcc=13V
15
1200 1100 1000
Vcc=13V RI= 13 Ohm
10 900 800 5 700 600 0 -50 -25 0 25 50 75 100 125 150 500 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
22/37
VND5E160AJ-E
Electrical specifications
Figure 29. CS_DIS high level voltage
Vcsdh (V)
4 3,5 3
Figure 30. CS_DIS clamp voltage
Vcsdcl(V)
10 9 8 7
Iin = 1 mA
2,5 2 1,5 1
6 5 4 3 2
0,5 0 -50 -25 0 25 50 75 100 125 150 175
1 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Figure 31. CS_DIS low level voltage
Vcsdl (V)
3
2,5
2
1,5
1
0,5
0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
23/37
Application information
VND5E160AJ-E
3
Application information
Figure 32. Application schematic
+5V
VCC Rprot CS_DIS Dld CU Rprot INPUT OUTPUT Rprot CURRENT SENSE GND RSENSE CEXT VGND RGND DGND
Note:
Channel 2 has the same internal circuit as channel 1.
3.1
GND protection network against reverse battery
This section provides two solutions for implementing a ground protection network against reverse battery.
3.1.1
Solution 1 : resistor in the ground line (RGND only)
This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1. 2. RGND 600mV / (IS(on)max) RGND (- CC) / (-IGND) V
where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum On-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are On in the case of several high side drivers sharing the same RGND.
24/37
VND5E160AJ-E
Application information
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
3.1.2
Solution 2 : diode (DGND) in the ground line
A resistor (RGND=1k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift ( 600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO 7637-2: 2004(E) table.
3.3
MCU I/Os protection
If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os: -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak = - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 180k Recommended values: Rprot =10k CEXT=10nF. ,
25/37
Application information
VND5E160AJ-E
3.4
Current sense and diagnostic
The current sense pin performs a double function (see Figure 33: Current sense and diagnostic):
Current mirror of the load current in normal operation, delivering a current proportional to the load one according to a know ratio KX. The current ISENSE can be easily converted to a voltage VSENSE by means of an external resistor RSENSE. Linearity between IOUT and VSENSE is ensured up to 5V minimum (see parameter VSENSE in Table 9: Current sense (8VA logic level high on CS_DIS pin sets at the same time all the current sense pins of the device in a high impedance state, thus disabling the current monitoring and diagnostic detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of sense resistance and ADC line among different devices. Figure 33. Current sense and diagnostic
VBAT VPU
VCC
Main MOSn
41V
PU_CMD Overtemperature
IOUT/KX ISENSEH CS_DIS
+
OL OFF
RPU
VOL
Pwr_Lim INPUTn
OUTn
ILoff2r ILoff2f
VSENSEH CURRENT SENSEn RPROT To uC ADC RSENSE GND RPD Load
VSENSE
26/37
VND5E160AJ-E
Application information
3.4.1
Short to VCC and OFF state open load detection
Short to VCC A short circuit between VCC and output is indicated by the relevant current sense pin set to VSENSEH during the device off state. Small or no current is delivered by the current sense during the on state depending on the nature of the short circuit. OFF state open load with external circuitry Detection of an open load in off mode requires an external pull-up resistor RPU connecting the output to a positive supply voltage VPU. It is preferable VPU to be switched off during the module stand-by mode in order to avoid the overall stand-by current consumption to increase in normal conditions, i.e. when load is connected. An external pull down resistor RPD connected between output and GND is mandatory to avoid misdetection in case of floating outputs in off state (see Figure 33: Current sense and diagnostic). RPD must be selected in order to ensure VOUT < VOLmin unless pulled up by the external circuitry:
VOUT
Pull - up _ OFF
= RPD I L ( off 2 ) f < VOL min = 2V
RPD 22 K is recommended. For proper open load detection in off state, the external pull-up resistor must be selected according to the following formula:
VOUT
Pull - up _ ON
=
RPD VPU - RPU RPD I L ( off 2) r RPU + RPD
> VOL max = 4V
For the values of VOLmin ,VOLmax, IL(off2)r and IL(off2)f see Table 10: Openload detection (8V27/37
Application information
VND5E160AJ-E
3.5
Maximum demagnetization energy (VCC = 13.5V)
Figure 34. Maximum turn-Off current versus inductance (for each channel)
100
10
A B C
1 I (A) 0,1 0,1 1 L (mH) 10 100
A: Tjstart = 150C single pulse B: Tjstart = 100C repetitive pulse C: Tjstart = 125C repetitive pulse
VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with RL = 0 . In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.
28/37
VND5E160AJ-E
Package and PC board thermal data
4
4.1
Package and PC board thermal data
PowerSSO-12 thermal data
Figure 35. PowerSSO-12 PC board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70m (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 36. Rthj-amb vs. PCB copper area in open box free air condition (one channel ON)
RTHj_amb(C/W)
70 65 60 55 50 45 40 0 2 4 6 8 10
PCB Cu heatsink area (cm^2)
29/37
Package and PC board thermal data
VND5E160AJ-E
Figure 37. PowerSSO-12 thermal impedance junction ambient single pulse (one channel ON)
ZTH (C/W)
100
Footprint 2 cm2 8 cm2
10
1 0,001
0,01
0,1
1 Time (s)
10
100
1000
Equation 1: pulse calculation formula Z TH =R TH +Z THtp ( 1 - )
where = tP/T Figure 38. Thermal fitting model of a double channel HSD in PowerSSO-12 (a)
a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
30/37
VND5E160AJ-E Table 13. Thermal parameters
Area/island (cm2) R1= R7 (C/W) R2= R8 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1= C7 (W.s/C) C2= C8 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C)
Package and PC board thermal data
Footprint 1.2 6 3 8 22 26 0.0008 0.0016 0.0166 0.2 0.27 3
2
8
8 15 20
7 10 15
0.1 0.8 6
0.1 1 9
31/37
Package and packing information
VND5E160AJ-E
5
5.1
Package and packing information
ECOPACK(R) packages
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
5.2
Package mechanical data
Figure 39. PowerSSO-12 package dimensions
32/37
VND5E160AJ-E Table 14. PowerSSO-12 mechanical data
Package and packing information
Millimeters Symbol Min. A A1 A2 B C D E e H h L k X Y ddd 5.800 0.250 0.400 0 2.200 2.900 1.250 0.000 1.100 0.230 0.190 4.800 3.800 0.800 6.200 0.500 1.270 8 2.800 3.500 0.100 Typ. Max. 1.620 0.100 1.650 0.410 0.250 5.000 4.000
33/37
Package and packing information
VND5E160AJ-E
5.3
Packing information
Figure 40. PowerSSO-12 tube shipment (no suffix)
B C
Base Q.ty Bulk Q.ty Tube length ( 0.5) 100 2000 532 1.85 6.75 0.6
A
A B C ( 0.1)
All dimensions are in mm.
Figure 41. PowerSSO-12 tape and reel shipment (suffix "TR")
REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4
TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing All dimensions are in mm. W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 12 4 8 1.5 1.5 5.5 4.5 2
End
Start Top cover tape No components Components 500mm min No components
500mm min Empty components pockets saled with cover tape. User direction of feed
34/37
VND5E160AJ-E
Order codes
6
Order codes
Table 15. Device summary
Order codes Package Tube PowerSSO-12 VND5E160AJ-E Tape and reel VND5E160AJTR-E
35/37
Revision history
VND5E160AJ-E
7
Revision history
Table 16.
Date 13-Sep-2004
Document revision history
Revision 1 Initial release. Document reformatted and restructured. Updated Figure 2: Configuration diagram (top view) : pins 7-12 left unconnected (N.C) . Updated Table 9: Current sense (8V14-Mar-2008
2
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VND5E160AJ-E
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